1. Field of the Invention
Aspects of the invention generally relate to the fabrication of semiconductor devices and to chemical mechanical polishing and planarization of semiconductor devices.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lay at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity for conductors and materials having low dielectric constant (low k, defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the functioning of semiconductor devices.
One conductive material gaining acceptance is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), higher current, and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper-containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e., vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper-containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper-containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper-containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed.
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in dual damascene processes to remove excess deposited material and to provide an even surface for subsequent levels of metallization and processing. Planarization may also be used in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing article in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing article. The article is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing article while dispersing a polishing composition to effect both chemical activity and mechanical activity.
Conventionally, in polishing copper features, such as dual damascene features, the copper-containing material, and a portion of the barrier layer, is polished to the level of the barrier layer, and then the barrier layer is polished, with a portion of the dielectric layer and copper features, to a level of the underlying dielectric layer. However, conventional polishing processes often result in uneven removal of the copper features and the dielectric layer resulting in the formation of topographical defects, such as concavities or depressions in the copper features, referred to as dishing, and excess removal of dielectric material surrounding the copper features, referred to as erosion.
FIG. 1 is a schematic view of a substrate illustrating the phenomenon of dishing. Conductive lines 11 and 12 are formed by depositing conductive materials, such as copper or copper alloy, in a feature definition formed in the dielectric layer 10, typically comprised of silicon oxides or other dielectric materials. After planarization, a portion of the conductive material is depressed by an amount D, referred to as the amount of dishing, forming a concave copper surface. Dishing results in a non-planar surface that impairs the ability to print high-resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper.
An additional difficulty also arises when using low k dielectric material in copper dual damascene formation. Low k dielectric materials are typically soft, porous, and brittle. Current polishing pressures, about 4 psi or greater, can damage the low k dielectric material and form defects in the substrate surface such as film delamination due to high shear stress caused by the friction between the polishing pad and substrate surface.
One proposed solution to reduce dishing and polish low k dielectric material with reduced defect formation is to polish substrates at reduced polishing pressures. However, polishing substrates at reduced pressures often results in less than desirable polishing rates, non-uniform polishing, and less than desirable planarization of the substrate surface. Such undesirable processing of the substrate surface may also result in reduced substrate throughput and less than desirable polish quality of the substrate surface. Additionally delamination has also been observed to occur at reduced polishing pressures.
Additionally, low polishing pressure processes may be unable to sufficiently remove all of the desired copper materials from a substrate surface such as at the interface between copper and the barrier layer, which is generally non-planar. The remaining copper materials, or residues, can detrimentally affect device formation, such as creating short-circuits within or between devices, reduce device yields, reduce substrate throughput, and detrimentally affect the polish quality of the substrate surface.
Therefore, there exists a need for an apparatus and method that reduce or minimize the formation of topographical defects and film delamination during processing.